DEEP RESEARCH · HBM4 · PIM · MEMORY POWER SHIFT

HBM4 and PIM — Memory Makers Move from Supporting Cast to Lead

Base dies are becoming logic; compute is moving inside memory. The result: a margin flip between TSMC and the memory three.

Published: 2025-12-26 · Semiconductor value-chain reordering · Original Naver Blog post

0. Bottom line first

• HBM: Bandwidth. From HBM4, the base die requires logic-foundry process — memory grows a "brain."
• CXL: Capacity and pooling. Memory is freed from a specific CPU; data centers become memory-centric.
• PIM: Compute-in-memory. For inference, ~2× the perf of GPU and 70–85%+ better energy efficiency.
• Neuromorphic: Brain-like, memory and compute fuse at the device level — Von Neumann ends.
• Profit battle: SK Hynix × TSMC "one team" vs. Samsung IDM turnkey. CoWoS is TSMC's last big moat.

1. Von Neumann is breaking — the memory wall and the energy crisis

Today's machines physically separate compute (CPU/GPU) and memory (DRAM). The bigger AI models get, the more time is spent ferrying data across that bus rather than computing.

Official fact: Recent studies show 60–80%+ of AI-compute energy is consumed in moving data between memory and processor — not in compute itself.

Interpretation: "Stop burning energy on data movement — compute inside the memory" is the PIM philosophy and a declaration that memory makers will become intelligent compute devices, not just storage.

1.1 SoC evolution — chiplets and heterogeneous integration

AI-era SoCs can no longer be monolithic (yields collapse, costs explode, memory bandwidth caps perf). The answer: chiplets + heterogeneous integration — combine chips made on best-fit nodes inside one package. TSMC's CoWoS (Chip-on-Wafer-on-Substrate) is the centerpiece, using a silicon interposer to wire logic and HBM side-by-side with thousands of times more I/O than a standard substrate. This is where memory makers either bond with or compete directly with logic foundries.

2. The roadmap — HBM → CXL → PIM → Neuromorphic

2.1 HBM — bandwidth revolution + logic invasion

HBM stacks DRAM vertically via TSV to massively grow I/O. Through HBM3E it was a "higher and faster" memory race. HBM4 (the 6th gen) changes the paradigm.

Official fact: The HBM4 base die is no longer made on a memory process; it is built on a 12 nm or 5 nm foundry logic process to drive the 2048-bit interface and host new control/compute logic.

2.2 CXL — capacity unleashed

If HBM solves speed, CXL solves capacity and efficiency. Built on PCIe, it lets memory expand like external storage and lets multiple CPUs share a giant memory pool. Samsung's CMM-D (CXL Memory Module) is positioning as a data-center TCO play.

2.3 PIM — compute meets storage

Integrate ALUs/NPUs inside memory and minimize data movement. Samsung HBM-PIM and SK Hynix GDDR6-AiM are the standard-bearers, particularly powerful for LLM inference (data access > heavy compute).

Official fact: PIM-equipped systems report energy-efficiency gains of 70–85%+ versus GPU baselines.

Interpretation: Once PIM ships at scale, memory companies pivot from "selling bits (capacity)" to "selling performance" — becoming accelerator vendors that take a slice of logic's TAM.

2.4 Neuromorphic — the end of Von Neumann

Memory and compute fuse at the device level (memristors etc.), mimicking synapses. Intel Loihi and IBM NorthPole lead the early research. At this point the physical line between memory and logic chips disappears.

3. TSMC vs. the memory three — the fight for the base die

3.1 Where the profit pool is moving

Through HBM3E, memory makers built base dies on their own DRAM processes. HBM4 changes that — the base die is now a "brain" running the memory controller plus extra functions, and it needs 12/5 nm logic.

Official fact: SK Hynix is raising HBM4 prices by over 50% vs HBM3E (to ~$500–600), absorbing higher base-die and packaging costs to defend profitability.

Interpretation: The pie grows, but a meaningful slice is shared with TSMC. If Samsung can internalize the foundry cost, it gets a structural cost edge — recent flexibility on "using TSMC base dies if customers want" signals pragmatic positioning to recapture HBM share, not pride.

3.2 The Margin Flip — a historic inversion

Official fact: Historically TSMC ran 50%+ gross margins while memory swung with the cycle. 4Q25 forecasts now put SK Hynix and Samsung memory gross margins at 63–67%, overtaking TSMC's ~60%.

• Driver: HBM sells at 5–7× regular DRAM; AI demand outstrips supply, putting pricing power in memory makers' hands.
• Meaning: Memory has transitioned from commodity to specialty — NVIDIA is reportedly paying tens of trillions of won in prepayments to fund memory-maker capex.

3.3 TSMC's defense — CoWoS monopoly

NVIDIA's H100-class accelerators can't ship without TSMC's CoWoS. TSMC owns the chokepoint, absorbs a large chunk of unit cost, and extends "Foundry 2.0" (wafer + packaging + test + mask). CoWoS capacity is reportedly fully booked through 2026.

4. The future — PIM at scale and sovereign AI

4.1 Memory makers become platforms

Accelerators built on SK Hynix GDDR6-AiM or Samsung HBM-PIM are showing ~2× performance + 70%+ energy savings in LLM inference vs GPUs. That opens the door for memory companies to sell their own accelerators into data centers and on-device AI — moving from "components" to "platform solutions." Samsung and SK Hynix are already in talks with OpenAI and others on PIM-based custom AI silicon.

4.2 Sovereign AI and cost efficiency

Sovereign AI plus chronic NVIDIA shortage and pricing → demand for cost-efficient inference. LPDDR + PIM offers exactly that combination. This becomes another huge revenue pillar beyond HBM and a way to escape the TSMC-centric high-cost ecosystem.

5. Conclusion — interdependence + an intense fight for control