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What a 2027 Apple-Intel Foundry Partnership Would Mean

A semiconductor-supply-chain read on Ming-Chi Kuo’s 18A-P M-series report and Intel IDM 2.0 execution risk

Date: 2025-11-30 · Semiconductor supply-chain analysis · Naver Blog source and public articles

You are responsible for your own investment decisions. This material is research, not a recommendation to buy or sell.

0. Bottom line first

The core of the rumor is not Apple buying Intel CPUs again. It is whether Intel Foundry can manufacture Apple-designed M-series chips. Success would restore confidence in Intel 18A-P and IDM 2.0; failure would expose yield and execution limits again.

A different Apple-Intel relationshipFrom CPU supplier to potential foundry partner
AppleM-series design
Intel Foundry18A-P manufacturing candidate
TSMCExisting core partner
U.S. fabsGeopolitical hedge
The key milestones are 2026 risk production and 2027 yield stabilization.

1. The core of Kuo’s report

Official fact: The source says Ming-Chi Kuo posted on X and Medium on November 28, 2025 that Apple could use Intel’s 18A process for M-series chips from 2027. It also says Apple had signed an NDA, received Intel’s 18A-P PDK 0.9.1GA, and begun PPA simulations.

Interpretation: This matters because the claim includes engineering milestones such as PDK versions, tape-out, and risk production. But Apple evaluating a process is not the same as a committed mass-production contract.

TimingStageDetailsStatus
2H 2025Initial validationNDA, 18A-P PDK 0.9.1GA, PPA simulationDone/in progress
1Q 2026Design freezePDK 1.0/1.1 and tape-out preparationPlanned
2H 2026Risk productionPrototype validation of yield and performanceExpected
1H 2027Yield stabilizationRamp-up for HVMTarget
2Q-3Q 2027Potential shipmentPossible low-end M processor supplyAssumption

2. Technical issues: 18A-P and packaging

The source frames 18A-P, GAA, BSPDN, High-NA EUV, and Foveros Direct 3D as the technical backdrop. Sub-5-micron pitch 3D interconnect is presented as a potential weapon against TSMC if Apple moves further into chiplets or memory-on-logic stacking.

Process

18A-P

The Intel leading-edge foundry process reportedly under Apple evaluation.

Power

BSPDN

Backside power delivery aimed at improving power, performance, and area.

Packaging

Foveros Direct 3D

A dense 3D packaging option for connecting chips more like internal die structures.

3. Apple’s calculation

Official fact: The source says Apple’s chip production is heavily dependent on TSMC and Taiwan, and that using Intel’s U.S. fabs could provide a political and geopolitical hedge.

  • Supply-chain hedge: reduce Taiwan and single-point-of-failure risk
  • Negotiating leverage: signal an alternative to TSMC price increases
  • Capacity priority: move low-end M chips to Intel and reserve TSMC leading-edge capacity for higher-margin iPhone Pro or AI chips
  • Political insurance: align with CHIPS Act and U.S. manufacturing policy

4. Intel’s calculation

For Intel, Apple would not be just another customer; it would be an anchor tenant proving the credibility of the foundry business. The source says Intel shares rose more than 10% after Kuo’s report, with the market treating a possible Apple order as a turnaround signal.

Interpretation: Execution matters more than headlines. If Intel cannot prove 18A yield, customer-service culture, and a credible ecosystem versus TSMC, Apple can stop the project.

5. Risk scenarios

Yield

Yield miss

The source mentions outside rumors of sub-10% early 18A yield. Intel says progress is on track, but HVM remains unproven.

Ecosystem

TSMC gap

Transistor performance alone is not enough; IP, packaging, and thermal-management experience matter.

Culture

Foundry service model

A foundry must prioritize customer requirements. Intel’s shift from IDM culture is still the question.

6. My view

I read this less as Apple leaving TSMC and more as Apple adding a supply-chain option. For Intel, it is close to a last big proof point; for Apple, outsourcing part of a low-end M processor could reduce ecosystem risk. Until 2026 risk-production data appears, expectation and verification should be kept separate.

Sources

Naver original