DEEP RESEARCH · SEMICONDUCTORS · HBM4
HBM4 Landscape — Samsung vs SK hynix vs Micron
Process, packaging, yield, and roadmap — can Samsung's hybrid-bonding bet unseat SK hynix?
0. Bottom Line First
At HBM4 the three vendors converge on 12-Hi 36GB, 2048-bit interface, and ~2TB/s bandwidth. The differentiator is the 'process + packaging + base die' combo. SK hynix plays stability (1b + MR-MUF) to defend near-term share; Samsung swings (1c + hybrid bonding + in-house 4nm) for a 2026+ comeback. Micron locks in the third spot with a fast catch-up.
- SK hynix shipped industry-first HBM4 12-Hi 36GB samples in March 2025 and plans mass production in H2 2025. Q1 2025 HBM market share: ~70%.
- Micron formally announced HBM4 36GB samples in June 2025 — 7.85 Gbps, 2.0 TB/s, 20% better energy efficiency vs HBM3E.
- Samsung is shipping its first samples in July 2025, targeting 2026 mass production. 1c DRAM (~70% yield as of June 2025) + in-house 4nm base die + hybrid-bonded 16-Hi — applying multiple node leaps at once.
- Bloomberg Intelligence: HBM TAM US$2.3B (2024) → ~US$13B by 2030.
1. Spec Comparison — Converging on 12-Hi 36GB, Diverging on Base Die
HBM4 is the 6th generation, after HBM, HBM2/2E, HBM3, and HBM3E. The interface doubles from 1024 to 2048 bits, and all three vendors target ~7.8 Gbps/pin to deliver 2 TB/s.
| Item | Samsung HBM4 | SK hynix HBM4 | Micron HBM4 |
|---|---|---|---|
| DRAM process | 10nm-class 6th gen (1c)1 | 10nm-class 5th gen (1b) | 1β (1-beta) |
| DRAM die capacity | 24Gb (expected)2 | 24Gb (36GB at 12-Hi) | 24Gb (36GB at 12-Hi) |
| Stack height & capacity | 16-Hi (target 48GB)3 | 12-Hi 36GB (production); 16-Hi 48GB in 2026 | 12-Hi 36GB sample; 16-Hi after |
| Interface width | 2048-bit (JEDEC) | 2048-bit (JEDEC) | 2048-bit (16ch × 128b) |
| Per-pin speed | ~7.8 Gbps (expected)4 | ~7.8 Gbps (expected) | 7.85 Gbps (sample) |
| Total bandwidth | ≥ 2.0 TB/s | ~2.0 TB/s | 2.0 TB/s (sample) |
| Base die (logic) | Samsung 4nm (in-house) | TSMC 5nm (outsourced) | TSMC 12FFC+ or 5nm |
| Key feature | Hybrid bonding for 16-Hi; custom HBM push | Advanced MR-MUF for 12/16-Hi; power & base-die gains | BIST built-in for integration ease |
1 Samsung 1c is reportedly EUV-based ~12nm class; SK 1b ~14–15nm class. 2 All three use ~24Gb dies for 12-Hi 36GB. 3 Samsung's 2025 samples focus on 16-Hi. 4 JEDEC HBM4 caps near 8 Gbps/pin.
Official fact: Starting at HBM4, the base die evolves from a simple signal pass-through into a 'smart' logic-bearing die. SK hynix officials state that HBM4 12-Hi development targets base-die performance gains and lower power draw.
Interpretation: The spec sheets look similar, but who fabs the base die determines cost, performance, and differentiation. Samsung leverages its IDM advantage (memory + foundry) by using in-house 4nm. SK and Micron rely on TSMC, making TSMC capacity a swing variable for their roadmaps and costs.
2. Packaging — MR-MUF vs TC-NCF vs Hybrid Bonding
MR-MUF — One-Shot Underfill
Bond dies via microbumps, then inject liquid underfill into the gaps in a single step and cure. Introduced in 2019. Uniform fill and good thermal dissipation. Advanced MR-MUF fits 16-Hi HBM4 within JEDEC's 775µm height limit.
TC-NCF — Per-Layer Film
Bond each layer with a non-conductive film and thermal compression. Higher per-layer precision but longer takt time. Micron sticks with TC-NCF for HBM4 due to cost-vs-maturity tradeoffs.
Hybrid Bonding — Bumpless Cu-Cu
Direct chemical bonding of metal pads + oxide surfaces (Cu-Cu). Eliminates microbumps, enables <10µm pitch, cuts resistance/parasitics and chip-to-chip spacing. Fits more stacks within the same height and dissipates heat better.
Official fact: In an ECTC 2024 paper Samsung argued hybrid bonding is 'essential for 16-Hi and beyond,' and reported a working 16-Hi HBM test chip using its captive equipment subsidiary (Semes). SK hynix calls hybrid bonding a 'backup option' for now, citing equipment cost and fab-footprint issues.
Interpretation: Classic 'incumbent vs. disruptor' setup — SK locks in yield with proven flow, Samsung bets on a structurally superior process for the long arc. Early ramp-yield and cost on hybrid bonding remain the swing factor; customers carry adoption risk if early quality slips.
3. Yield & Share — 'Stable SK' vs 'Process-Bet Samsung'
Q1 2025 HBM market share: SK hynix ~70%, with Samsung and Micron splitting the rest. The result of SK near-monopoly supply of HBM3 to NVIDIA AI GPUs in 2024. HBM carries 3–5× the margin of commodity DRAM, so the company that masters stable mass production captures outsized profit.
From SK's vantage, MR-MUF cures underfill in one shot, helping uniform fill and thermal-stress relief at higher stack counts. 12-Hi HBM4 samples have shipped without issue and ramp is on schedule. TC-NCF, by contrast, accumulates per-layer alignment error and underfill voids; Samsung learned that the hard way during HBM2E and lost share.
Official fact: As of June 2025, Samsung's 1c DRAM yield is reported around 70%, with full ramp prep into year-end. SK hynix is concentrating on 1b capacity expansion (e.g., the M15X fab in Icheon) and has slowed 1c equipment buys. TrendForce 2024 HBM share estimate: SK ~52% (up) / Samsung ~42% (slightly down).
Interpretation: SK's choice is a rational 'cash the current generation' play; Samsung's choice is an aggressive 'leapfrog a generation in one move.' Yield curves at 2026 ramp will decide which call ages better.
4. Samsung's New Toolbox — Hybrid Bonding + Custom Base Die
① Hybrid Bonding Payoff
- Lower stack height: Removing microbumps lets 17 chips (1 logic + 16 memory) fit within JEDEC's 775µm — even opens the door to 24-Hi in future generations.
- Better thermals: No bumps shortens the chip-to-chip thermal path and widens the conduction surface — easier heat removal at HBM4 data rates.
- Signal integrity: Direct Cu bonding eliminates impedance bumps and parasitics that microbumps add — stable transmission at 2× bus width and higher Gbps.
- Risks: Early-ramp yield, equipment cost, customer trust. A captive equipment subsidiary partially offsets the cost burden.
② Custom Logic Die — IDM Synergy
Samsung exploits its IDM (memory + foundry) advantage by fabbing the logic base die in-house on 4nm. SK considers TSMC 5nm sufficient; Samsung's 4nm leaves more room for higher clocks and lower power. SK plans to introduce 1c DRAM + 5nm logic only from HBM4E (next-next gen); Samsung tries the 1c + 4nm combo already at HBM4.
Official fact: On custom HBM — SK hynix is co-developing 'HBM4E' customizations with NVIDIA, Microsoft and others. Samsung is in talks with Broadcom and AMD on tailored HBM. Micron has signaled customizable base dies starting at HBM4E.
Interpretation: HBM has stopped being a pure bandwidth race — it is becoming a contest of integrated AI/HPC solutions. Samsung leads on process and pushes customization hard to win the non-NVIDIA pool (AMD, Google TPU, etc.).
5. Roadmap & Market Outlook
- SK hynix: Mass production of HBM4 in late 2025 → HBM4E in H2 2026; 1c DRAM + TSMC 5nm logic enter at HBM4E.
- Samsung: First samples July 2025 → mass production H1 2026; eyes a leap at HBM5 once hybrid-bonding maturity is in hand.
- Micron: 2025 sample → 2026 mass production. Adding EUV and expanding Boise capacity. Says 2025 HBM volume is 'fully sold out.'
- TAM: Bloomberg Intelligence — US$2.3B (2024) → ~US$13B by 2030; 30–40%+ CAGR. HBM adoption is spreading beyond GPUs to CPUs, AI accelerators, and networking ASICs.
SK hynix's stable process plus entrenched customer base likely keeps it in the lead through 2025–2026. If Samsung's bigger bet (hybrid bonding + node lead) clears its yield ramp from 2026, the leaderboard can reshuffle. Micron solidifies the third spot while the whole pie grows. For Samsung's gambit to pay off, it must clear ramp yield AND convince anchor customers — both at once.
Sources
- Original Naver Blog post: https://m.blog.naver.com/PostView.naver?blogId=star_of_self&logNo=223913716949
- Trade-press coverage and company disclosures (TrendForce HBM share estimates, Samsung ECTC 2024 paper, Bloomberg Intelligence HBM TAM, official statements from SK hynix, Samsung, and Micron — footnoted in the original).