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DEEP RESEARCH · Silicon photonics

Optical Semiconductors and Silicon Photonics: Reading the Bottleneck Through CPO, COUPE, and SoIC

A study note on optical conversion, advanced packaging, and hybrid-bonding ecosystems for reducing chip-to-chip bottlenecks

Written: 2024-12-30 · Semiconductor technology study · Naver Blog

You are responsible for your own investment decisions. This material is research and is not a recommendation to buy or sell.

0. Bottom line first

Chip-to-chip connection is always a bottleneck. Silicon photonics, which converts electrical signals into light, and CPO, which brings that optical engine into the processor package, are technologies I need to keep watching in AI data centers and high-performance computing.

Article image about TSMC building an optical semiconductor supply chain

Official fact: The linked article title says TSMC has opened the competition in optical semiconductors and is building a broad cooperation system. The article summary says TSMC is building a supply chain ahead of next year’s mass production, while Samsung Electronics and Intel are also expected to enter the market.

1. Relationship between silicon photonics and CPO

AI data-center bottleneckChip-to-chip data movement speed and power consumption
Electrical signalLimits of conventional transmission
Silicon photonicsConverts electrical signals into light
CPOIntegrates XPU and optical engine in one package
Efficiency gainLower power consumption and latency
Goal: high-speed, high-efficiency data processing
  • Silicon photonics is a technology that transmits data by converting electrical signals into light.
  • CPO, or Co-Packaged Optics, integrates a processor or XPU and an optical engine in one package to improve data-transfer efficiency.
  • Silicon photonics is a core technology for implementing CPO, while CPO minimizes the physical distance between the processor and optical engine to maximize data-transfer efficiency.

2. How TSMC COUPE connects with SoIC

COUPE

Compact Universal Photonic Engine

TSMC’s CPO platform integrates electronic integrated circuits, or EICs, and photonic integrated circuits, or PICs, through SoIC-X chip packaging.

SoIC

System on Integrated Chips

TSMC’s 3D stacking technology uses TSVs without micro-bumps to stack chips vertically and implement high-speed connections.

Connection

Dense integration of optics and electronics

COUPE uses SoIC hybrid bonding to integrate electronic and photonic ICs, improving data-transfer efficiency and reducing power consumption.

Reference image on TSMC packaging and silicon photonics roadmap

Reference image on TSMC 3D-SoIC core technology

3. Hybrid bonding process and equipment

StepCore contentRelated equipment
PreparationDeposit insulators and copper wiring on wafers and dies, planarize the surface with CMP, then treat the surface through plasma activationCMP and cleaning equipment, metrology equipment
BondingBond aligned wafers and dies at a set temperature to form bonding between insulating layersHybrid bonders and nanometer-level precision metrology tools
AnnealingAfter bonding, use hydrogen annealing to increase bonding strength and remove gapsAnnealing equipment
DicingSeparate the wafer into individual diesLaser dicing equipment

4. Major company trends

  • NVIDIA entered silicon photonics through its 2020 acquisition of Mellanox and is developing silicon photonics technology for AI data centers in cooperation with TSMC and Broadcom.
  • TSMC provides silicon-photonics-based packaging solutions through COUPE and SoIC and is expanding applications in AI and high-performance computing, or HPC.
  • Corning supplies silicon-photonics-related components based on optical glass and fiber technology, and the note summarizes a view that Optical revenue will begin in earnest from 2025.

Interpretation: As efficiency improvement becomes more important in data centers and AI computing environments, silicon photonics and related equipment are likely to become more important.

Reference image on OFC 2024 and the CPO era

Reference image on practical timing for CPO technology

Reference image on TSMC advanced packaging technology

5. Additional references

I am keeping these references on silicon photonics, CPO, SoIC, glass substrates, and FO-PLP together. This topic should be read as a shift toward solving data-movement bottlenecks with packaging and optical conversion, not only with front-end process scaling.

Reference image explaining silicon photonics

Reference image on silicon photonics and glass substrates

Reference image for an easy explanation of silicon photonics

Reference image on TSMC 3D-stacked semiconductor technology

Reference image on differences between Samsung Electronics and TSMC FO-PLP strategies

Sources

Naver original